Field of the Invention
The present invention relates to a display device.
Discussion of the Related Art
With the development of information society, various demands for display devices for displaying picture images have been increasing. In this respect, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) device have been recently used.
The display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes data lines, gate lines, and a plurality of pixels formed at crossing portions between the data lines and the gate lines and supplied with data voltages of the data lines when gate signals are supplied to the gate lines. The pixels emit light with a predetermined brightness in accordance with the data voltages. The gate driver supplies the gate signals to the gate lines. The data driver includes source drive integrated circuits (hereinafter, referred to as “ICs”) that supply the data voltages to the data lines. The timing controller controls an operation timing of each of the gate driver and the data driver.
For example, the gate driver may be formed in a non-display area of the display panel in a gate driver in panel (GIP) mode. In this case, the gate driver includes stages having a plurality of transistors, and supplies gate signals for swinging a gate high voltage and a gate low voltage to the gate lines in accordance with a start signal and gate clock signals input from the timing controller.
Display devices with UHD (ultra-high definition, 3840×2160) has been recently launched. Since the charging time of a data voltage charged in each of pixels is not sufficient in the display device of UHD, a gate driver supplies gate signals in such a manner that pulse widths of the gate signals supplied to adjacent gate lines are overlapped with each other. In this case, since pulse widths of adjacent gate clock signals are overlapped with each other, pulse widths of a start signal and gate clock signals are wider. Particularly, the number of line memories for delaying image data supplied from a timing controller to a data driver increase because the pulse width of the start signal is wider. The manufacturing cost may increase due to increase of the number of line memories.